An image sensor generally includes an array of pixel cells. Each pixel cell includes a photo-conversion device for converting light incident on the array into electrical signals. An image sensor also typically includes peripheral circuitry for controlling devices of the array and for converting the electrical signals into a digital image.
FIG. 1 is a top plan view block diagram of a portion of a typical CMOS image sensor 10. The image sensor 10 includes an array 11 of pixel cells arranged in columns and rows (not shown). The array 11 includes pixel cells 20 (FIG. 2A) in an active array region 12 and pixel cells 20′ in a black region 13. FIG. 2A is a schematic diagram of typical pixel cells 20 and FIG. 2B is a top plan view of a pixel cell 20. The black pixel cells 20′ have the same structure and operate in a similar manner to the active array pixel cells 20. Accordingly, black pixel cells 20′ can be configured as shown in FIG. 2A.
The black region 13 is similar to the active array region 12, except that light is prevented from reaching the photo-conversion devices of the black pixel cells 20′ by, for example, a metal layer, a black color filter array, or any opaque material (not shown). Signals from black pixel cells 20′ can be used to determine the black level for the array 11, which is used to adjust the resulting image produced by the image sensor 10.
The pixel cells 20 illustrated in FIGS. 2A and 2B are typical CMOS four-transistor (4T) pixel cells. Typically, the pixel cells 20 are formed at a surface of a substrate (not shown). The substrate is doped to a first conductivity type, e.g., p-type and is biased at a ground potential. As is known in the art, a pixel cell 20 functions by receiving photons of light and converting those photons into charge carried by electrons. For this, each one of the pixel cells 20 includes a photo-conversion device 21, which is shown as a pinned photodiode, but can be a photogate, photoconductor, or other photosensitive device. The photodiode 21 includes an n-type photodiode charge accumulation region 22 and a p-type surface layer (not shown).
Each pixel cell 20 also includes a transfer transistor 27, which receives a transfer control signal TX at its gate 27a. The transfer transistor 27 is connected to the photodiode 21 and a floating diffusion region 25. During operation, the TX signal operates the transfer transistor 27 to transfer charge from the photodiode charge accumulation region 22 to the floating diffusion region 25.
The pixel cell 20 further includes a reset transistor 28, which receives a reset control signal RST at its gate 28a. The reset transistor 28 is connected to the floating diffusion region 25 and includes a source/drain region 60 coupled to a voltage supply, Vaa-pix, through a contact 23. In response to the RST signal the reset transistor 28 operates to reset the diffusion region 25 to a predetermined charge level, Vaa-pix.
A source follower transistor 29 has a gate 29a coupled to the floating diffusion region 25 through a contact 23 that receives and amplifies a charge level from the diffusion region 25. The source follower transistor 29 also includes a first source/drain region 60 coupled to the power supply voltage, Vaa-pix, and a second source/drain region 60 connected to a row select transistor 26. The row select transistor 26 receives a row select control signal ROW_SEL at its gate 26a. In response to the ROW_SEL signal, the row select transistor 26 couples the pixel cell 20 to a column line 22, which is coupled to a source/drain region 60 of the row select transistor 26. When the row select gate 26a is operated, an output voltage is output from the pixel cell 20 through the column line 22.
Referring again to FIG. 1, after pixel cells of array 11 generate charge in response to incident light, electrical signals indicating charge levels are read out and processed by circuitry 15 peripheral to array 11. Peripheral circuitry 15 typically includes row select circuitry 16 and column select circuitry 17 for activating particular rows and columns of the array 11; and other peripheral circuitry 18, which can include analog signal processing circuitry, analog-to-digital conversion circuitry, and digital logic processing circuitry. Peripheral circuitry 15 can be located adjacent to the array 11, as shown in FIG. 1.
In order to obtain a high quality image, it is important to obtain an accurate black level for the array 11. One problem encountered in the conventional image sensor 10 is interference from the active array region 12 with the black region 13. When very bright light is incident on active array pixel cells 20 adjacent to the black region 13, blooming can occur and excess charge from the active array pixel cells 20 can travel to and interfere with black pixel cells 20′ in the adjacent black region 13. Additionally, excess charge from adjacent circuitry, e.g., peripheral circuitry 15, can travel to and interfere with pixel cells 20′ in the adjacent black region 13. This can cause inaccurate black levels and distortion of the resultant image.
One solution to the above noted problem is to provide buffer pixel cells 20″ within the black region 13 and adjacent the black pixel cells 20′, as shown in FIG. 2C. FIG. 2C depicts a portion of rows of the array 11. Typically, the buffer pixel cells 20″ have a similar structure to the black pixel cells 20′ and the active array pixel cells 20. During operation of the image sensor 10, the signal output from the buffer pixel cells 20″ is discarded. As shown in FIG. 2C, multiple rows 14b of buffer pixel cells 20″ are provided flanking (i.e., on two sides) the rows 14a of black pixel cells 20′. In this manner, the buffer pixel cells 20″ act as a spacer to distance black pixel cells 20′ from active array pixel cells 20 and other devices that can cause interference. Even with buffer pixel cells 20″, however, interference with black pixel cells still occurs.
Accordingly, it would be advantageous to have an improved image sensor with reduced interference between active and black pixel cells.